1. Field of the Invention
The present invention is directed generally to the field of integrated circuits and, more particularly, to the generation of clock signals for controlling the operation of such circuits.
2. Description of the Background
Many high-speed integrated circuit devices, such as synchronous dynamic random access memories (SDRAM), microprocessors, etc. rely upon clock signals to control the flow of commands, data, addresses, etc., into, through, and out of the devices. Additionally, new types of circuit architectures such as RAMBUS and SLDRAM require individual parts to work in unison even though such parts may individually operate at different speeds. As a result, the ability to control the operation of a part through the generation of local clock signals has become increasingly more important.
Typically, operations are initiated at the edges of the clock signals (i.e., transitions from high to low or low to high). To more precisely control the timing of operations within the device, each period of a clock signal is sometimes divided into subperiods so that certain operations do not begin until shortly after the clock edge.
One method for controlling the timing of operations within a period of a clock signal generates phase-delayed versions of the clock signal. For example, to divide the clock period into four subperiods, phase delayed versions are produced that lag the clock signal by 90.degree., 180.degree. and 270.degree., respectively. Edges of the phase-delayed clock signals provide signal transitions at the beginning or end of each subperiod that can be used to initiate operations.
An example of such an approach is shown in FIGS. 1 and 2A-2F where the timing of operations in a memory device 10 is defined by an externally provided control clock reference signal CCLKREF and an externally provided data clock reference signal DCLKREF. The reference clock signals CCLKREF, DCLKREF are generated in a memory controller 11 and transmitted to the memory device 10 over a control clock bus 13 and a data clock bus 14, respectively. The reference clock signals CCLKREF, DCLKREF have identical frequencies, although the control clock reference signal CCLKREF is a continuous signal and the data clock reference signal DCLKREF is a discontinuous signal, i.e., the data clock reference signal DCLKREF does not include a pulse for every clock period T, as shown in FIGS. 2B and 2E, respectively. Although the reference clock signals CCLKREF, DCLKREF have equal frequencies, they may be phase shifted by a lag time T.sub.L upon arrival at the memory device 10 due to differences in propagation times, such as may be produced by routing differences between the control clock bus 13 and the data clock bus 14.
Control data CD1-CDN (FIG. 2A) arrive at respective input terminals 16 substantially simultaneously with pulses of the control clock reference signal CCLKREF and are latched in respective control data latches 18. However, if the device attempts to latch the control data CD1-CDN immediately upon the edge of the control clock reference signal CCLKREF, the control data may not have sufficient time to develop at the input terminals 16. For example, a voltage corresponding to a first logic state (e.g., a "0") at one of the input terminals 16 may not change to a voltage corresponding to an opposite logic state (e.g., a "1") by the time the data are latched. To allow time for the control data CD1-CDN to fully develop at the input terminals 16, the control data are latched at a delayed time relative to the control clock reference signal CCLKREF. To provide a clock edge to trigger latching of the control data CD1-CDN at the delayed time t.sub.1, a delay circuit 20 delays the control clock reference signal CCLKREF by a delay time T.sub.D1 to produce a first delayed control clock signal CCLKD (FIG. 2C). Edges of the first delayed control clock signal CCLKD activate the control data latches 18 to latch the control data CD1-CDN at time t.sub.1.
Data DA1-DAM (FIG. 2D) arrive at data terminals 22 substantially simultaneously with the data clock reference signal DCLKREF (FIG. 2E). Respective data latches 24 latch the data DA1-DAM. As with the control data CD1-CDN, it is desirable that the data DA1-DAM be latched with a slight delay relative to transitions of the data clock reference signal DCKLREF to allow time for signal development at the data terminals 22. To provide a delayed clock edge, a delay circuit 26 delays the data clock reference signal DCLKREF (FIG. 2E) to produce a phase-delayed data clock signal DCLKD (FIG. 2F) that is delayed relative to the data clock reference signal DCLKREF by the delay time T.sub.D2.
For latching both control data CD1-CDN and data DA1-DAM, it is often desirable to allow some adjustment of the phase delay. For example, if the clock frequencies change, the duration of the subperiods will change correspondingly. Consequently, the delayed clock signals CCLKD, DCLKD may not allow sufficient signal development time before latching the control data or data, respectively. Also, variations in transmission times of control data, data, or clock signals may cause shifts in arrival times of control data CD1-CDN or data DA1-DAM relative to the reference clock signals of the memory device 10.
One possible approach to producing a variable delay is for the control clock generator to employ a delay-locked loop 28 driven by the control clock reference signal CCLKREF, as shown in FIG. 3A. The control clock reference signal CCLKREF is input to a conventional multiple output variable delay line 30 such as that described in Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits 31(11):1723-1732, November 1996. The delay line 30 is a known circuit that outputs multiple delayed signals CCLK1-CCLKN with increasing lags relative to the control clock reference signal CCLKREF. The delays of the signals CCLK1-CCLKN are variably responsive to a control signal Vcon received at a control port 32.
A feedback loop, formed by a comparator 34 and an integrator 36, produces the control signal Vcon. The feedback loop receives the control clock reference signal CCLKREF at one input of the comparator 34 and receives one of the output signals CCLKN from the delay line 30 as a feedback signal at the other input of the comparator 34. The comparator 34 outputs a compare signal Vcomp that is integrated by the integrator 36 to produce the control signal Vcon.
As is known, the control signal Vcon will depend upon the relative phases of the control clock reference signal CCLKREF and the feedback signal CCLKN. If the feedback signal CCLKN leads the control clock reference signal CCLKREF, the control signal Vcon increases the delay of the delay line 30, thereby reducing the magnitude of the control signal Vcon until the feedback signal CCLKN is in phase with the control clock reference signal CCLKREF. Similarly, if the feedback signal CCLK lags the control clock reference signal CCLKREF, the control signal Vcon causes the delay line 30 to decrease the delay until the feedback signal CCLKN is in phase with the control clock reference signal CCLKREF. A similar delay-locked loop 37 produces the delayed data clock signals DCLK1-DCLKN in response to the data clock reference signal DCLKREF as shown in FIG. 3B.
As the circuitry for generating the clock signals becomes more and more complex, the delay associated with that circuitry becomes greater and greater. Furthermore, process variations and operating temperatures affect the circuitry generating the clock signals causing the delay to vary. Such a variable delay reintroduces some of the same problems that the clock generation circuitry is designed to eliminate. Thus, there is a need for clock generation circuitry that compensates for the variable delay introduced by the clock generation circuitry itself.